Statistical prediction of circuit aging under process variations

Accurate prediction of circuit aging and its variability is essential to reliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on compact models of transistor degradation and circuit performance, we develop analytical solutions that efficiently predict the statistics of both circuit timing and the leakage under temporal stress and process variations. These solutions prove that circuit aging and its variance can be fully predicted from the characteristics of transistor degradation and circuit performance sensitivity to aged parameters, independent on the type and the amount of process variations. Specific results include: (1) under variations, the standard deviation of circuit speed declines with the stress time, following a power law of 1/6; and (2) the logarithmic mean and the standard deviation of leakage current decrease with the stress time as t1/6. The results are systematically validated by simulation and measurement data from an industrial 65 nm technology, enhancing the predictability and efficiency of statistical reliability analysis.


Introduction
With relentless scaling of CMOS technology, circuit timing uncertainty due to temporal degradation and static process variations poses a dramatic challenge to IC design (International Technology Roadmap for Semiconductors, 2008;Reddy et al., 2002;Nassif, 2001;Lin et al., 1998). The deterioration of circuit performance over time, i.e., aging, is usually caused by several physical mechanisms such as channel-hot-carrier (CHC), negative-biastemperature-instability (NBTI), and time-dependent-dielectric-breakdown (TDDB) (Schroder & Babcock, 2003;Alam & Mahapatra, 2005;Wang et al., 2007;Vattikonda et al., 2006;Ogawa et al., 2003). Among these effects, NBTI is the leading mechanism that is responsible for the majority part of circuit aging (Kimizuka et al., 1999;Wang et al., 2007). In (Wang et al., 2007), the authors show that for 65nm technology, CHC degradation is much smaller than NBTI degradation, almost one order lower in the degradation magnitude. NBTI primarily increases the threshold voltage (V th ) of PMOS devices. Such parameters shift significantly affects circuit lifetime and performance (e.g., power, speed and failure rate), and in the worst case, may even result in a complete parametric failure of a system (Borkar, 2006;Alam & Mahapatra, 2005;Wang et al., 2007;Vattikonda et al., 2006;Bhardwaj et al., 2006;Kumar et al., 2006;Paul et al., 2006). To cope with this threat and guarantee circuit lifetime, it is critical to include NBTI into circuit analysis and adaptively develop design techniques to effectively mitigate its negative impact on performance. For a VLSI design, an accurate prediction of circuit performance degradation under NBTI remains as a tremendous challenge. As shown in (Wang et al., 2007), NBTI has a strong dependence on dynamic operation conditions, such as supply voltage (V dd ), temperature (T) and input signal probability (α s ). Usually these parameters are not spatially or temporally uniform, but vary significantly from gate to gate and from time to time. Similar to the burnin process, we may use high voltage and high temperature to guardband the worst case condition. However, the search for the worst case α s is computationally inhibitive due to the extremely large space of signal probabilities for each input node. A practical method is proposed to predict the upper bound of each gate under all possible input α s s (Agarwal et al., 2008). Besides these uncertainties, static process variation poses another challenge that leads to the variance of circuit aging. Fig. 1 illustrates an example that shows the statistical measurement of switching frequency and the leakage (IDDQ) of ring oscillators (ROs) before the reliability test. In this 65nm technology, more than 3X and 25% variability are observed in circuit leakage and the speed, respectively. These variabilities are attributed to statistical distributions of device parameters that are caused by the manufacturing process (Nassif, 2001). Examples include dopant concentration, channel length (L), oxide thickness (t ox ), etc. Their impact on device and circuit performance is usually investigated through a reduced set of device parameters -V th is the most important one among them, as the interface between process and electrical studies. In (Liu et al., 2007), we have identified that the leading variation sources are L, V th and carrier mobility (μ). By including the extracted variations of these three sources in the nominal model file, we are able to accurately predict the change of IV characteristics in all regions. Other variations, such as that in t ox , are included into these variations (e.g., V th is a function of t ox ) and indirectly affect device performance. Since NBTI effect has an exponential dependence of V th (Wang et al., 2007;Alam & Mahapatra, 2005;Wang et al., 2007), circuit aging strongly interacts with process variations, significantly shifting both the mean and the variance of the circuit performance. By focusing on this primary variation source -V th , we are therefore able to gain key insights and project the first-order trend. Other secondary process sources are neglected in this work. With the availability of more detailed data in the future, we will incorporate more sources. Fig. 2 shows the measured speed degradation from the same set of ROs as those in Fig. 1. Circuit performance and its variability not only depend on static process variations, but also change over the period of dynamic operation because of the effect of circuit aging (Schroder & Babcock, 2003;Wang et al., 2007). Therefore, accurate prediction of circuit performance distribution during its life time should consider the impact of static variations, primary reliability mechanisms, and more importantly, their interactions. This prediction is essential for designers to safely guardband the circuit for a sufficient life time. Otherwise, we have to either use an overly pessimistic bound, or resort to expensive stress tests in order to collect enough statistical information.
www.intechopen.com A few works have been published in the literature to estimate the statistical variations in temporal NBTI degradation (Rauch, 2002;2007;Rosa et al., 2006;Kang et al., 2007). Their assumption is the number of broken bonds in the channel is a Poisson random variable, and correspondingly V th follows the Poisson distribution. With technology scaling, additional V th variations, such as random dopant fluctuation and short channel effects, need to be considered. The measurement data show that the distribution of V th variations follows the Gaussian distribution (Liu et al., 2007). In addition, the correlations between process variation and NBTI are ignored in previous work. In this work, we begin with the assumption that process variation induced V th change is Gaussian random variable. We leverage compact models of transistor degradation and circuit performance to achieve accurate and efficient reliability prediction. Dynamic NBTI effect is incorporated into the analytical framework to account for the aging of circuit speed and the leakage (Schroder & Babcock, 2003;Wang et al., 2007). Based on our initial observation with the available data, the specific contributions and conclusions of this work include: • A statistical predictive methodology of circuit aging is proposed. In this analytical approach, only five model parameters need to be extracted from fresh data (i.e., before the stress). With the initial information of the transistor and circuit topology, these models provide accurate prediction of circuit performance degradation and the variability.

•
The degradation rate of circuit speed and its standard deviation follows a power law of 1/6. While the mean of circuit timing goes up with the stress time, the variance actually declines due to the interaction between NBTI effect and process variations. The degradation rate of both values is independent on the amount and the type of variations in the circuit.

•
The mean and the standard deviation of logarithmic IDDQ reduce with the stress time as t 1/6 , with the variance more sensitive to global variations.

•
A hierarchical statistical aging analysis methodology is proposed to efficiently predict circuit aging under both process variations and operation uncertainties.
The outline of the paper is as follows: In Section 2, the statistical modeling for both transistor and circuit performance degradation is described, and the proposed models are comprehensively verified with silicon data from industrial 65nm technology, as well as SPICE simulation results. Section 3 presents a hierarchical statistical aging analysis methodology for circuit performance prediction. Finally Section 4 concludes this work.

Statistical modeling of circuit aging
NBTI is the dominant effect of circuit aging in advanced CMOS technology (Schroder & Babcock, 2003;Kimizuka et al., 1999). We propose a hierarchical solution to bridge the underlying device physics with efficient circuit analysis. Based on the reaction-diffusion mechanism, we developed the model of Vth shift under NBTI effect. In the presence of process variations and aging, using Gradual Change Approximation (GCA), this model is further expanded as a linear function of Vth shift to efficiently predict the performance degradation.
To characterize the change of circuit performance under the stress, the Alpha-power law based delay model and the leakage model are calibrated for a given gate. Under the condition that the amount of NBTI-induced V th shift is much smaller than the nominal value of V th , both models are simplified to extract the dependence of circuit performance to V th change. Finally, the gate-level models are integrated into various circuit paths to analytically predict the aging of path timing and the leakage. Both the mean value and the variance of these important metrics are derived as a function of static performance variability, the nominal sensitivity of circuit performance, and other operation conditions, such as supply voltage and temperature.

Gradual change approximation
NBTI manifests itself in a gradual increase in the magnitude of PMOS threshold voltage, resulting in the degradation of circuit performance over time. A set of publications have shown that NBTI is only pronounced in a long term, i.e., the performance degradation of transistors and circuits is a gradual aging process (Kumar et al., 2006;Wang et al., 2007). ΔV th in different devices due to variation and NBTI is still a relative small portion compared to the nominal V th value. Thus, when we derive the statistical degradation model, the first order Taylor expansion (i.e., linear expression) is applicable to transistor and circuit metrics, such as Equations (1) and (2), as well as gate delay and leakage analysis. This is the Gradual Change Approximation (GCA), which can be applied to simplify the following model derivations. (1) (2)

Transistor degradation model
NBTI occurs when a negative gate bias is applied to the PMOS devices and it has two phases: stress and recovery (Alam & Mahapatra, 2005;Wang et al., 2007). In stress phase, the www.intechopen.com holes in the channel weaken the Si-H bonds, which results in the generation of the positive interface charges and hydrogen species. During recovery phase, the interface traps are annealed by the hydrogen species and thus, V th degradation (ΔV th-nbti ) is partially recovered. Two main theories are proposed to interpret NBTI degradation: Reaction-Diffusion (RD) (Alam & Mahapatra, 2005;Alam et al., 2007;Krishnan et al., 2005) and hole Trapping/ Detrapping (T/DT) (Shen et al., 2006;Parthasarathy et al., 2006;Huard et al., 2006). R-D model naturally explains the long-term power law time exponent of NBTI (n ~1/6) Wang et al., 2007;Bhardwaj et al., 2006). However, the experimental data obtained by using on-the-fly (OTF) measurement Rangan et al., 2003), or ultra-fast (UF) measurement (Reisinger et al., 2006) show that the power law dependence with a time exponent of n > 1/6. R-D model cannot explain well the fast transient in the beginning of recovery of NBTI. Thus, we introduce an experimental term to capture the behavior of the fast response in recovery (Bhardwaj et al., 2006;Wang et al., 2007), and the long-term ΔV th-nbti is given by, (4) where T clk , α s , and n are clock period, input signal probability, and time exponential constant (1/6), respectively. K, ξ 1 , ξ 2 and E 0 are fitting parameters. K v describes the dependence of the bias voltage, T, t ox and other technology parameters associated with NBTI degradation (Bhardwaj et al., 2006;Wang et al., 2007). For more details about the meaning and value of the parameters, please refer to (Bhardwaj et al., 2006;Wang et al., 2007). The dependence of NBTI effect on V th (which is a parameter lumping many process details) is still under the debate. For instance, reference (Alam & Mahapatra, 2005) has discussed several possibilities. A general observation is that NBTI is strongly affected by the electric field. Under the stress condition, this field is proportional to (V gs -V t )/t ox , which leads to our model. By so far, this model matches data from 180nm down to 45nm, making it a generic model to describe NBTI effect in technology scaling. We are further collecting data from multi-V th technology at the same technology node, with the target to verify it with more process details. Fig. 3 verifies this model with one set of experimental data under different stress conditions. Besides this long term prediction model, both static and real time dynamic models are also available in (Bhardwaj et al., 2006;Wang et al., 2007). The models well capture NBTI recovery effect (Agarwal et al., 2008). This model assumes nominal degradation without considering the statistical process variations. If there are global and local process variations, V th in Equation (5) should be expressed as: where V th0 is the nominal threshold voltage, ΔV th-g and ΔV th-l represent the change of threshold voltage due to global and local variations, respectively. Equation (6) shows that positive variation results in V th increase, which correspondingly leads to smaller V th degradation (according to Equations (3) and (5)), while negative variation results in larger V th degradation. Fig. 4 shows V th degradation over time for three different transistors. Due to process variations, Device 1 starts with a larger V th and Device 3 starts with a smaller V th . Substitute their fresh V th to Equations (3) -(5), ΔV th for these three devices is shown as Fig. 4. At the beginning, the difference in V th degradation between Device 1 and Device 3 is 20.97%. With the increase of stress time, the difference becomes smaller and smaller. After 10 5 s stress, it decreases to 15.57%. Such a compensation between process variations and aging is well captured by our model. Since the degradation rate of different circuit paths is pronouncedly different due to different switching activities and circuit topologies (Wang et al., 2007), in (Agarwal et al., 2008), we introduce a Maximum Dynamic Stress (MDS) simulation technique with α s www.intechopen.com approaching to 1, which gives a simple and realistic estimation of the upper limit of gate delay degradation under dynamic NBTI. By using GCA and MDS described in (Agarwal et al., 2008), the long term prediction model is further simplified as a variation dependent model, i.e., where the value of A depends on both technology parameters and operating conditions; S v is the nominal sensitivity of NBTI degradation to V th shift. In this work, A = 2.5 × 10 -3 V/s 1/6 and S v = 7V -1 . Fig. 5 validates this simplified model (Equation (7)) with the long term predictive model (Equations (3) - (5)) under different process variations. Within ±30mV, it provides accurate prediction of V th degradation. Besides V th change, carrier mobility also degrades with increasing stress time (Wang et al., 2007). According to the universal effective mobility model, the dominant components of carrier scattering are phonon scattering, surface roughness scattering, and coulomb scattering. Aging effects induced interface charges result in stronger column scattering, which affects the carrier mobility mostly in low V gs region. Because of this reason, mobility degradation is more important for analog circuit aging, but not for digital circuits. This behavior has been confirmed by the 65nm data (Wang et al., 2007). Thus, in this work, since the analysis is focused on digital circuit in which the devices operate at saturation region, the mobility degradation is ignored.

Gate delay degradation model
A widely used gate delay (T di ) model is based on the Alpha-power law that was proposed in (Sakurai & Newton, 1990), where C li is the effective load capacitance of the gate; β i is a parameter depending on gate size. Under both process variations and NBTI effect, V thi of PMOS is given by www.intechopen.com (9) Substituting V thi into Equation (8) and using the GCA of 1/(1x) p ≈ 1+ p · x (for x 1), we obtain: , which is the gate delay without process variations and NBTI degradation (ΔV thi = 0), and S ti = α/(V dd -V th0 ), which is the nominal sensitivity of gate delay to PMOS V th shift. These two parameters rely on the process technology and the circuit structure. They can be conveniently extracted from SPICE simulation at the nominal condition. Thus, Equation (11) becomes: Substitute Equations (7) and (10) into (12), Since 65nm measurement data show that the distribution of V th variation is Gaussian distribution (Nassif, 2001;Liu et al., 2007), in this work, we assume ΔV thi-g and ΔV thi-l are Gaussian random variables. Their mean (μ g and μ l ) are 0 and their standard deviations (σ g and σ l ) depend on the manufacturing process (Borkar et al., 2003). Since gate delay is linearly proportional to the threshold voltage change, the probability distribution function (PDF) of gate delay also follows the normal distribution At t = 0, ΔV th-nbti = 0. Assuming global and local variations are uncorrelated random variables (Boning & Nassif, 2001), and are given by: At t > 0, from Equation (13), we get (15) Given the initial conditions of the process and timing information for the transistor and the gate, Equation (15) predicts the mean and standard deviation with increasing time. From these equations, we have four observations: 1. The mean of gate delay increases with the stress time, while the variance decreases. Since a lower-V th transistor has a faster degradation rate and thus, larger V th increase, this phenomenon compensates static process variations and reduces the variance during the stress period. 2. As the stress time increases, the aging of both mean and standard deviation follows the same power law of t 1/6 . 3. The degradation rate of gate delay and its variance are independent of the amount and the type of variations.
www.intechopen.com 4. The degradation rate is determined by the sensitivities to V th shift. Process variations only affect the fresh variability, but not the degradation rate.

Circuit performance degradation model 2.4.1 Path timing
The PDF of a path comprising n gates corresponds to the linear combination of the n PDFs of gate delays. The mean and the variance of the path delay (T d ) are given by (16) where ρ ij is the correlation coefficient between two gates. For the simplicity of the demonstration, we assume the inter-gate correlation is the same for all the gates, i.e., ρ ij = ρ, while this methodology is general enough for all statistical conditions. Thus, the variance of path delay is derived as (17) In the case of local variations, ρ = 0, i.e., the variations between two gates are uncorrelated. The case of ρ = 1 describes global variations, i.e., the variations between two gates are correlated. With both local and global variations, is given by the linear combination of the variance of the local and global variations. Fig. 6 shows the delay distribution of ROs due to circuit aging. The distribution of gate delay becomes increasingly narrower under the stress as indicated by Equation (15).    Fig. 7).

Leakage
IDDQ of a circuit is defined as the total amount of leakage current at the standby. It has an exponential dependence on V th : where m is the body effect coefficient and v T is the thermal voltage (kT/q). Substitute Equation (10)  Under global variations, using Equation (7), Equation (20) becomes the following (21) The mean and standard deviation of circuit leakage are (22)   (23) where Under local variations, Equation (20) is approximated as (24) where η has the value between 0 and 1, depending on the circuit structure. The mean and standard deviation of circuit leakage are (25) Akin to path timing, logarithmic IDDQ has the same time dependence under either global or local variation. Their impact is only different by a factor of η, which is derived from the circuit structure. Fig. 9 shows that the logarithmic mean and the standard deviation degradation of leakage current follow the power law of t 1/6 . The mean is relatively independent of the type of variations, while standard deviation is more sensitive to the global variation.

Statistical aging analysis
The analysis above generates the statistics of each gate under the aging effect. In reality, the distributions of logic gates in a circuit are correlated depending on their statistical properties. To obtain the information of path timing degradation, we can incorporate statistical timing analysis techniques to handle the correlation. In this section, we propose a hierarchical method to extract related model parameters and prepare the framework for the integration. Fig. 10 shows the statistical circuit performance analysis flow which is used to predict the circuit performance. This flow incorporates conventional static timing analysis with the statistical properties of the circuit and the process technology. The primary components include:

Model parameter extraction. Given technology and operating condition information, A
and S v are extracted. Given standard cell performance library, T d0i , IDDQ i and S t are extracted. For more details about parameter extraction, please refer to (Wang et al., 2007) and Section 3.2.1. 2. Substituting all the parameters into Equations (13), (21) and (24), we obtain the aged standard cell performance library. The cell timing and leakage are functions of transistor global and local V th variations and stress time.
3. Generating two statistical distribution of transistor fresh V th variations, one is for global variation and the other is for local variation. Their means are 0, and standard deviations are determined by the manufacturing process. 4. Given circuit netlist, random assign V th variations from the generated distribution to each transistor. With specified V th variations, the cell timing and leakage of the aged standard cell library are only function of stress time. 5. Given stress time, using circuit performance analyzer with the aged standard cell library, we get the circuit performance degradation. For example, we want to do timing analysis for given circuit. Since the aged library provides each cell timing information, the path timing is obtained by adding up all the individual cell timings in the path. We can do leakage analysis in the same way. 6. For circuit performance distribution prediction, given initial V th variation distribution, Equations (16), (17), (22), (23), (25), (26) directly give the mean and standard derivation of circuit performance distribution.

Model prediction and silicon validation 3.2.1 Model parameter extraction
In order to accurately predict the circuit performance degradation, there are five parameters need to be characterized at t = 0, including: A, S v , S t , T d0i and IDDQi. A: Parameter of long term V th degradation under nominal conditions. Its value is extracted from Equations (3) -(5), with the dependence of temperatures, V dd , and switching activity.
S v : the sensitivity of NBTI-induced transistor degradation to the nominal value of V th . S t : the sensitivity of gate delay to PMOS V th shift. T d0i : nominal gate delay, without V th variation and aging. IDDQi: nominal gate leakage, without V th variation and aging. Note these parameters are all extracted from the nominal condition, but not affected by process variations. Variations only change the distribution of T d and IDDQ, which can be obtained from the statistics at t = 0 (i.e., before the stress). During the stress, the interaction between variability and reliability follows the prediction of our new models. These statistical reliability models improve the predictability in the design stage, avoiding expensive reliability test at the circuit level.

Test chip and measurement
To validate the statistical models for the circuit performance, an inverter ring oscillator was designed as the prototype circuit (Reddy et al., 2002). Fig. 11 shows the simplified schematic of the ring oscillator. The channel length of the transistors in the ring oscillator is drawn at the minimum design rule. There is a NAND gate that allows the RO oscillation enable/disable (OE pin). When the oscillation is disabled, i.e., OE = 0V, IDDQ is measured through V RING . When the oscillation is enabled, i.e., OE = V dd , the RO oscillates at full speed (several GHz) and Ring Oscillator Frequency (Fosc) is measured periodically without any interruptions. Similar as the on-the-fly measurement at the device level, this dynamic stress measurement is nonstop. In this work, the ROs are stressed under various supply voltage and temperature conditions. The temperature was the same for both stress and measurement and no electrical stress was applied until the temperature was at the proper value.
www.intechopen.com Fig. 11. Simplified schematic of inverter ring oscillator circuit. Oscillation is disabled by grounding the Oscillation Enable (OE) pin.

Model validation with silicon data
The proposed statistical model is verified by 65nm technology available silicon data under a few operating conditions. Fig. 12 shows the delay degradation of ROs. The dots present the mean changes; the error bars are scaled delay distribution of the sample circuits; and the lines are the model predictions. While the mean value increases as t 1/6 , as a signature of the dominance of NBTI effect in circuit aging, the distribution declines with stress time. Fig. 13 evaluates the change of both the active current (IDDA), and the leakage current (IDDQ).
Since IDDA ≈CV/ f, for given switching frequency, IDDA is easily extracted. Our predictive models only require the sensitivities of transistor and circuit aging, as well as the statistics before the stress. Then the degradation of circuit performance is fully predicted toward the end of the life time.

Simulation setup of circuit benchmarks
The statistical aging analysis has been implemented in C to predict the circuit performance degradation of ISCAS85, 89 and ITC99 benchmark circuits (, n.d.; ITC99 Benchmark, n.d.). We  obtain an aging aware library by running SPICE simulation using PTM 65nm technology (Zhao & Cao, 2006 -Vincentelli, 1992) using this standard library. Random local and global variations are generated from a Gaussian distribution with mean 0 and standard deviation which is determined by the manufacturing process. The delay of each gate is calculated at time = 0 (with the variations) and after 10 years (with variations and NBTI degradation) using the aging aware library. Timing analysis is then performed, and the path delay for each path is calculated as the sum of the individual gate delays. After the run, the path with the maximum delay is identified as the critical path in the design. Figures 14 and 15 show the path delay distribution under both NBTI effect and process variation with time increasing. From these two figures, it can be seen that the mean of the path delay increases, while the standard deviation of the path delay decreases. Both of them follows the power law dependence of t 1/6 . As shown in the figure, at t = 0, the delay difference between maximum and minimum is 10.18%, while after 10 years stress, it reduces to 5.29%. The Path delay degradation caused by NBTI effect for 10 years stress is 14.06%, which is more than the delay difference caused by process variations at t = 0. Thus, for the circuit designers, it is critical to consider both NBTI effect and process variation at the early design stage.   Based on the simulation results of Table 1, we have three observations. 1. For most circuits, NBTI-induced delay degradation is comparable or larger than the process variations-induced delay difference. For example, circuit K2, after 10 years stress, NBTI-induced delay degradation is 15.65%, while the delay difference caused by process variation at Time = 0 is 13.22%. Thus, for circuit designers, it is necessary to add a guardband for NBTI in addition to guardband for process variations. 2. The impact of process variations on circuit delay strongly depends on the circuit structure.

Results and discussions
For instance, at Time = 0, process variation-induced delay difference for circuit Frg2 is 33.09%, while it is 4.97% for circuit Apex6. This effect is seen at Time = 10 years also. 3. The mean of the circuit delay increases with time, while the standard deviation decreases. Both of them follow the NBTI power law of t 1/6 and are independent of process variations (Fig. 14 and Fig. 15). By integrating the gate-based dynamic stress bound and process variation prediction model into circuit timing analysis, we verify that our hierarchical method provide a safe and tight bound of circuit timing degradation. Fig. 16 is the netlist of benchmark circuit C17. Fig. 17 shows the delay distribution of circuit C17 under various input vectors and process variations. As shown in the figure, the proposed method provides a safe and tight bound in the estimation of the circuit timing degradation, which helps to improve design predictability and avoid pessimistic guardbanding under NBTI effect.

Impact of statistical variations on SRAM
The six transistor SRAM (6T SRAM) design is highly sensitive to process variations, especially local random variations. The mismatch between neighboring transistors reduces the cell Static Noise Margin (SNM) (Krishnan et al., 2006;Lin et al., 2006;Rosa et al., 2006). The impact of statistical variations on SRAM SNM is mainly divided into Read, Write, and Hold stability. Under the NBTI effect, a weaker PMOS transistor increases Read failures, but improves the Write operation (Krishnan et al., 2006;Lin et al., 2006). Fig. 18 shows the PDF of 6T SRAM Read noise margin during the aging. In the SRAM cell, only one side of PMOS www.intechopen.com is stressed (i.e., with the gate biased at the ground), and the PMOS in the other side remains in the recovery. The mismatch in the stress mode reduces Read noise margin on one side, with no impact on the other side. As shown in Fig. 18, the mean value of Read noise margin decreases with longer aging time. Since Read SNM is determined only by the stressed PMOS side, NBTI induced SNM degradation is not cancelled out between stressed PMOS side and unstressed PMOS side. Therefore, the tail of Read SNM is determined by the stressed PMOS side. This behavior is different from the aging effect in a logic path, where random variability in each stage is averaged in the path timing. Further studies on statistical aging modeling are needed to predict the nonlinear behavior in SRAM.

Conclusions
In this work, a statistical methodology is developed to predict circuit performance degradation under both NBTI effect and process variations. These analytical solutions reveal that the degradation rate and its standard deviation are independent on the type and the amount of process variations. In order to predict the mean and the variance of circuit aging, only the characteristics of transistor degradation and circuit performance sensitivity to aged parameters are required. The aging of circuit speed and IDDQ shows a power law dependence on the stress time, as an evidence of the dominance of NBTI effect. The proposed method is implemented into SPICE simulation and timing analysis tools. With verification with 65nm silicon data, it supports statistical aging analysis in standard design flow, improving design predictability and helping avoid pessimistic guardbanding under the increasingly severe aging effect. We are collecting a larger volume of statistical data to further verify these conclusions.

Acknowledgements
This project is supported by SRC, Task  The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book.