Design Considerations for the Digital Core of a C1G2 RFID Tag

An EPC Class 1 Gen 2 (C1G2) RFID system is composed of a reader and one or several passive tags. Passive tags obtain the required energy from the radio frequency field emitted by the reader. The forward data link (reader to tag) is embedded in this radio frequency field. The backward data link (tag to reader) is achieved by means of backscattering. The RFID tag consists of several analog circuits and a digital core. The analog circuits perform tasks such as harvesting the energy from the electronic wave, supplying power, generating a clock signal and signal conditioning. The digital core of the tag performs data detection and implements the logical requirements of the standard.


Introduction
An EPC Class 1 Gen 2 (C1G2) RFID system is composed of a reader and one or several passive tags. Passive tags obtain the required energy from the radio frequency field emitted by the reader. The forward data link (reader to tag) is embedded in this radio frequency field. The backward data link (tag to reader) is achieved by means of backscattering. The RFID tag consists of several analog circuits and a digital core. The analog circuits perform tasks such as harvesting the energy from the electronic wave, supplying power, generating a clock signal and signal conditioning. The digital core of the tag performs data detection and implements the logical requirements of the standard. Fig. 1 shows the basic architecture of a long range Ultra High Frequency (UHF) RFID tag. The antenna receives the signal emitted by the reader. The voltage multiplier rectifies the incoming signal and increments the voltage to charge the supply capacitor C supply . The efficiency of this voltage conversion will depend on the architecture of the voltage multiplier. The supply capacitor is used to supply power to the rest of the tag. The analog front-end creates the signals that the rest of the tag needs to work properly, such as regulated voltages, the clock signal and the reset signal. It performs some kind of demodulation by generating an intermediate signal that can be used by the digital core to detect the received bits. The analog front-end also modulates the load impedance of the tag commanded by the digital core, to backscatter the signal emitted from the reader so that information can be transmitted backwards. The digital core handles the communication protocol and accesses the non volatile memory to retrieve and store data. Fig. 1 also shows the basic architecture of the digital core of a passive long range UHF tag. The input signal provided by the front-end is evaluated in a symbol detector to detect incoming symbols. A command decoder determines the operation code and the arguments received and it forwards them to a control unit. In the control unit, the finite state machine defined in the standard is implemented to control the communication flow. Moreover, depending on the standard, additional features such as collision arbitration algorithms or integrity checks are performed in this unit. Usually, the number of states of the finite state machine and the integrated additional features define the complexity and functionality of the whole tag. Finally, a transmitter controls the load modulator of the front-end and backscatters the answer to the reader. The C1G2 standard (EPC Global, 2005) has become the main communication protocol of passive long range UHF RFID systems. Given the success of the C1G2 standard, the ISO organization finally adopted it with minor changes as the ISO18000-6C (ISO, 2006). Nowadays, it is the dominant air interface for passive UHF RFID tags, because of its flexible functionality and the compatibility with the whole EPC network. Almost every recent research work concerning passive long range UHF RFID tags uses this communication protocol; e.g.: (Yan et al., 2006;Barnett et al. 2007;Man et al., 2007;Ricci et al., 2008;Zhang et al., 2008;Roostaie et al. 2008;Wanggen et al. 2009). Thus, this chapter is focused in the C1G2 standard. However, the concepts and ideas presented can be extended to other standards.

Communication range
The communication range of an RFID system is one of the factors that define the scope of its applications. Assuming that the reader is continuously sending a continuous wave (CW), the maximum communication distance between a passive RFID tag and the reader is mainly limited by two factors related to the tag's power consumption: the input power in the tag, and the voltage at the input of the voltage multiplier (Pardo et al., 2007;De Vita et al., 2005).

Input power in the tag
The communication range r is limited by the minimum input power. According to (Pardo et al. 2007 where P EIRP is the Effective Isotropic Radiated Power, λ the wavelength, G the tag antenna gain, X the reactance introduced by the load modulator, η the efficiency of the rectifier, R A the impedance of the antenna and P TAG the tag power consumption. Equation (1) shows that reducing the power consumption of the analog or digital parts increases the communication range.
Voltage at the input of the voltage multiplier According to (Pardo et al. 2007), there is another constraint due to the minimum voltage at the input of the voltage multiplier. If the threshold voltage required to switch on the voltage multiplier is not achieved, the tag will not start working, no matter the available input power. This constraint is related to the fabrication technology and it is given by where Q MN is the quality factor of the matching network and V tech is the minimum voltage at the input of the voltage multiplier. The voltage V tech depends on the technology used. Q MN can be expressed in terms of the equivalent input resistance of the tag as where R P is the equivalent resistance in parallel with C supply that represents the power consumption of the tag. R P increases as power consumption decreases. Thus, as the power consumption decreases, Q MN increases and a larger communication range is feasible. Summarizing, the communication range increases when the power consumption of the tag decreases. As detailed in (Pardo et al. 2007), the most restrictive of (1) and (2) sets the actual communication range of the system. However, the relation between power reduction and range improvement is not always constant. The dependence of the communication range on the input power in the tag is stronger than on the voltage at the voltage multiplier. Thus, when the power consumption of the tag is high and (1) limits the communication range, reducing the power consumption of the tag increases notably the maximum communication distance. But when the power consumption goes down, (2) becomes the most restrictive and the range improvement slows down. At this point the technology is limiting the communication more than the power consumption. A proper design of the tag is required to minimize the power consumption, and move from the section where the power consumption limits the communication range to the section where the technology is the limiter. This way, the maximum communication range for the selected technology can be achieved. As the digital part's power consumption can be comparable to the analog, the reduction of the digital power consumption is very important for the overall performance of the system. The main goal of the publications focused on C1G2 digital cores is to minimize the average power consumption. Advances in the technology of semiconductors help to reduce the power consumption of integrated circuits. Designers have to work with the technology available at that time. However, there are issues where designers can focus to optimize their designs for a given technology. The power consumption of the digital core grows with the clock frequency. Thus, designers try to reduce the clock frequency to minimize power consumption. Impinj, a C1G2 tag seller, published a white paper where this value was said to be 1.92MHz (Impinj, 2006). Even though there are some works in the literature that work at 1.92MHz, such as (Wang et al., 2007), most works propose digital cores for other clock frequencies. For example, (Hong et al., 2008) works at 4 MHz, (Man et al., 2007) at 3.3MHz, (Zhang et al. , 2008;Yan et al., 2006) at 1.28MHz and (Ricci et al., 2008) at 2MHz. A study of the constraints on the clock signal of the digital core is needed so that the clock frequency can be optimally selected. Another approach employed by digital designers to reduce power consumption is power management. Depending on the technology, similar benefits can be obtained in a simpler way by means of clock gating. In either case, the net effect is that the digital core can not be considered to have constant power consumption, but a power consumption profile in time (Zalbide et al., 2008). The effect of the shape of this power consumption profile in the overall performance (i.e.: communication range) needs to be studied.

Objectives of the chapter
This chapter performs an analysis of the EPC C1G2 standard to extract requirements of the tag's digital core for proper forward-link data detection and backward-link data backscattering. The EPC C1G2 standard specifies the characteristics of the waveforms employed in the forward-link communication. These characteristics of the waveforms pose requirements on the clock signal used for data detection (wander and jitter of the clock). The backscattering signal is also controlled by the digital core. Therefore, the requirements set by the standard on the backscattering signal constrain the clock signal used in the digital core as well. The chapter reviews some aspects of the operation of the digital core of the tag and presents equations and figures that can be used to select an appropriate clock signal.
On the other hand, the chapter presents methods to analyse the influence of the application of power management techniques in the communication range of the system. The results provide valuable tools to analyse different trade-offs early in the design of a RFID tag. The chapter is organized as follows. Section 2 describes the architecture of the digital core considered for the study. Section 3 analyses the constraints on the clock signal and Section 4 studies the influence of the power management on the communication range. Finally, the main conclusions are summarized in Section 5.

Architecture
Fig. 2 depicts the architecture of a generic C1G2 digital core used as example for this study. The incoming symbols are detected in the symbol detector. The command decoder obtains the operation code and the arguments of the requested operation. In order to avoid a big input buffer, the variable length arguments, such as the selection mask, are processed in the command decoder. The cryptographic functions are also performed in the command decoder making all arguments transparent to the rest of modules. The control module controls the system with a finite state machine and a register bank. The collision arbitration, session management and memory lock are contained in this module. It does the necessary operations accessing the memory and the register bank. Finally, TX, the transmitter, encodes the answer with the required format. For this purpose, a backward link frequency synthesizer is included in the transmitter. The accesses to the tag memory (EEPROM) are handled by an intermediate module memory access. The power management unit, PM, controls the activity of the rest of the modules using the clock gating technique. VEEPROM is a cache memory used to reshape the power consumption profile of the tag (Zalbide, 2009). For power management, five different working states have been defined. Every working state is optimized to perform a specific operation during the communication. Table 1 shows the relationship of the working states with the modules. Each working state activates the necessary modules to fulfill its functionality and deactivates the remaining modules. Some modules, such as the memory access, are used in various different working states; others are only used in a single working state. The combination of all the working states enables the system to work properly minimizing the activity of its circuitry. The STRTP state is the initial working state. The tag checks the kill bit, and if it is not killed, the system turns to STDBY state, waiting for the beginning of the forward link data www.intechopen.com  transmission. In this state only the symbol detector is active. When the beginning of a new message from the reader is detected, the command decoder is activated and the working state turns to RX. After receiving the whole message, the working state changes to CTRL, deactivating the command decoder and the symbol detector, and activating the control and the register bank. Finally, in the TX state the response is sent to the reader and the working state returns to STDBY. Reading from the EEPROM is one of the most power hungry operations that the tag performs. In the design presented in this chapter, the EEPROM is read when a lot of energy is arriving to the tag. Then, the read data is stored in VEEPROM, which is less power hungry. This way, if data from the EEPROM is needed when less energy is available, they can be read from VEEPROM instead of from EEPROM. The introduction of this module allows reshaping the power distribution so that the power peaks caused by the accesses to EEPROM can be moved to less critical time intervals. In exchange, the tag spends more time initializing, as it must copy the data from the EEPROM to the VEEPROM.

Analysis of the clock signal requirements
As the power consumption of the digital core grows with the clock frequency, the selection of a minimum clock frequency will maximize the communication range. In the following, a detailed study of the clock signal constraints for C1G2 communication is presented. This study shows that the minimum required clock frequency depends on the characteristics of of the clock signal and the implementation of the transmitter. The section is organized as follows. First, a model for the clock signal used by the digital core is defined. Then, the operation of the digital core is analyzed together with the specification of the standard. From this analysis, equations that constrain the clock signal parameters are obtained. These equations are computed numerically to find the regions in the clock signal parameter space where the C1G2 standard specifications are satisfied. These results facilitate the definition of the requirements for the generator of the clock signal used in the digital core.

Clock model
Ideally, the clock signal can be considered as a square wave of period T. The frequency, f=1/T, is assumed to be constant and invariable in time. Nevertheless, actual clock sources do not generate perfect clock signals. For instance, if we measure the average clock period over two time intervals in different days or ambient conditions, the results may be different. Moreover, the duration of the clock periods within the same time interval suffers small variations from one cycle to another. For our analysis, we will model the clock signal using two parameters: Average period, T a : it is the mean value of the period of the clock signal during a whole inventory round. Random jitter, ξ i : it is a random variable that represents the normalized deviation of the clock edges from the edges of the average period. Thus, the duration of the ith clock period T i is given by T i =T a +ξ i . If the maximum random jitter of the clock signal is annotated as ξ max , then for all i,

Forward link
In the forward link of C1G2 (EPC Global, 2005), a reader communicates with one or more tags by modulating a Radio Frequency (RF) carrier using Amplitude-Shift Keying (ASK) modulation with Pulse Interval Encoding (PIE). The reader transmits symbols of duration T S =T H +T L . In each symbol, the signal has maximum amplitude during T H seconds and minimum amplitude during T L seconds. T L =PW for both a data-0 and a data-1. As shown in Fig. 3, in order to transmit a data-0, T H is set so that T S =Tari. In order to transmit a data-1, T H is set so that 1.5·Tari ≤T S ≤2·Tari.

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The forward data rate is set in the preamble of every command sent by the reader to the tag by means of symbol RTcal, as shown in Fig. 4. The duration of this symbol RTcal is equal to the duration of a data-0 plus the duration of a data-1. A tag shall measure the length of RTcal and compute pivot=RTcal/2. The tag shall interpret subsequent reader symbols shorter than pivot as data-0s, and subsequent reader symbols longer than pivot as data-1s.

Symbol detection
The front-end of the tag is assumed to have a one bit Analog to Digital Converter (ADC) to convert the envelope of the RF signal to a digital signal. The input to the digital core is assumed to have a high value during T H and a low value during T L . The digital core samples the input signal and identifies the incoming symbols by measuring the distance between modulated pulses. It is assumed that one sample is taken every clock cycle. Given a generic symbol S, its duration will be annotated as t S . The number of samples obtained when sampling S, n S , will be in the range defined by equation (4).
where ⎣⋅⎦ and ⎡⋅⎤ are the floor and the ceil functions respectively.

Forward link constraints
For proper operation, the digital core shall be able to detect when its input signal is in the high and in the low states. The duration in the low state, PW, is the shortest one. Therefore, the first constraint is that n PW ≥1. From (4), the first constraint is obtained: The second constraint comes from the fact that in order to detect the data-0 symbol properly, If the symbol to be detected is a data-1, then we need that n data-1 >n pivot . Taking from (4) the minimum number of samples for n data-0 and the maximum number of samples for n RTcal , we obtain the third constraint:

Backward link
In the backward link, a tag communicates with a reader using ASK and/or Phase-Shift Keying (PSK) backscatter modulation (EPC Global, 2005). The backward link data codification can be either FM0 baseband or Miller. Both the backward link codification and data rate are set by the reader in the last Query command. The backward data rate is set by means of the duration of the TRcal symbol in the preamble and the Divide Ratio (DR) specified in the payload of the last Query command. A tag shall compute the backward link frequency as and adjust its response to be inside the Frequency Tolerance (FT) and Frequency Variation (FV) limits established by the C1G2 standard (EPC Global, 2005). Additionally, the standard sets requirements on the duty cycle of the backward signal.

TRcal symbol detection
The first source of error in the generation of BLF is introduced when symbol TRcal is detected. The digital core measures the duration of TRcal as the number of entire clock cycles comprised inside the backward link calibration symbol, n TRcal . The value of n TRcal will be an integer in the range given by (4). The value of n TRcal is used to compute the number of cycles required to synthesize one cycle of BLF. As n TRcal is an approximate representation of the duration of TRcal, an error will be introduced.

Backward link frequency synthesis
The accuracy of the synthesized backward link signal depends on how the transmitter is implemented. In the following, we analyze three possible implementations: balanced half-T pri base transmitter, unbalanced half-T pri base transmitter and full T pri base transmitter. A set of backward link constraints result for each of the three transmitters. For latter use, the following definitions are performed: • T pri =1/BLF is the period that the transmitter has to synthesize. • n Tpri is the number of clock cycles inside of a period of the synthesized backward link signal. • n H is the number of clock cycles that the transmitter maintains the output signal in high per period of the synthesized backward link signal. • n L is the number of clock cycles that the transmitter maintains the output signal in low per period of the synthesized backward link signal.

Balanced half-T pri base transmitter constraints
This is the most straightforward implementation of the transmitter using a synchronous digital circuit design flow. Inside the transmitter, a counter counts n H =n L clock cycles, and the output signal is toggled every time the counters finish. As n H and n L are the same, the output BLF signal stays the same number of cycles in high and in low, generating a balanced www.intechopen.com waveform. Thus, the transmitter needs to computes the number of cycles required to generate a half-T pri pulse. As this value has to be an integer, rounding is performed as shown in equation (9).
And thus, n Tpri =2n H . The average value of the synthesized backward link frequency will be n Tpri T a . Taking from equation (4) the maximum and minimum values of n TRcal , we can write the following two constraints to meet the frequency tolerance requirements of the standard: On the other hand, the frequency variation of the synthesized backward link signal is given by Taking into account that 11 (1 ) Tpri Tpri and manipulating equation (12), it can be shown that www.intechopen.com From the requirements in the standard, we find the frequency variation constraint ξ max < 0.0256.
This constraint is independent from the clock frequency: it only limits the maximum jitter. Finally, the duty cycle requirements are considered. The duty cycle can be expressed as 1

11
(1 ) (1 ) Introducing the worst case jitter values in (17) In this type of transmitter n H =n L , and equations (18) and (19) yield the same duty cycle constraint:

Unbalanced half-T pri base transmitter constraints
In this case, we also perform a synchronous digital circuit design flow, but we first compute the value of n Tpri as www.intechopen.com The counter in the transmitter counts n H clock cycles while the output is set to high, and n L clock cycles while the output signal is set to low. Proceeding in a similar way to the former transmitter, we find the two frequency tolerance constraints to be max 1 (1 ) The frequency variation constraint is the same as for the former transmitter and is given by (20). In this transmitter, the values of n H and n L are different. If we replace equations (22) and (23) in equations (18) and (19), we obtain the two duty cycle constraints. The backward link signal synthesized with this transmitter has a more accurate frequency. Nevertheless, the duty cycle is worse than in the former transmitter, because the number of cycles that the output signal is set to high and the number of cycles that the output signal is set to low can be different. This generates an unbalanced output waveform.

Full-T pri base transmitter constraints
This approach can be found in (Ricci et al., 2008). Part of the backward link signal synthesis is performed out of the digital circuit synchronous domain of the transmitter as shown in Fig. 5. The transmitter controls a multiplexer, which sets the output BLF signal to '1', '0', 'clk' or 'not clk'. With this technique, the time granularity needed by the transmitter is T pri instead of T pri /2, because the availability of 'clk' and 'not clk' makes it possible to toggle the input to the load modulator two times per clock cycle. Therefore, the values of n H and n L can take values with a precision of a half period: where n TPri is computed using equation (21). The frequency tolerance constraints for this transmitter are the same as for the former unbalanced half-T pri base transmitter and they are given by equations (24) and (25). The frequency variation constraint is equation (20), as for the two former transmitters. In order to analyze the duty cycle, we define n H (i) as the number of complete clock cycles that the signal is in high: and n H (f) as a variable that takes the value one when the signal has to be in high for half a clock cycle and cero when not; i.e.: () mod 2 f HH nn = .
Using these definitions, the duty cycle for this transmitter is given by The accuracy of the backward link signal synthesized with this transmitter is the same as for the former transmitter, but this transmitter has no negative effect on the duty cycle, as the synthesized output signal is balanced.

Results
In order to comply with all the C1G2 specifications, the clock signal has to fulfil all the presented constraints. As some of these constraints depend on the implemented transmitter type, in the following, the clock constraints are evaluated separately for the three transmitters. The results have been obtained sweeping the range of possible values of all the parameters. Tari, RTcal and TRcal have been swept with a resolution of 1μs for both values of DR. The resolution in 1/T a is of 1 kHz and of 0.1% in ξ max .
www.intechopen.com Fig. 6, Fig. 7 and Fig. 8 show the main constraints for a C1G2 digital core with a balanced half-T pri base transmitter, an unbalanced half-T pri base transmitter and a full-T pri base transmitter, respectively. The results are presented in a two dimensional plot, where the horizontal axis represents 1/T a and the vertical axis represents ξ max . The forward link curve separates the (1/T a , ξ max ) combinations that violate any of the forward link constraints from the (1/T a , ξ max ) combinations that satisfy all of them. For the backward link, the constraints have been plotted separately, so that we can better see their effect in the clock source requirements. Any combination (1/T a , ξ max ) inside the filled area fully complies with all the C1G2 clock requirements. Given a value of ξ max , several ranges of compliant values of 1/T a are found. The clock source implemented in the design has to generate a clock signal whose frequency is inside this range and its jitter is lower than the maximum allowed for the selected range. If we analyse Fig. 6, we can observe that, for a digital core with a balanced half-T pri base transmitter, it is possible to satisfy the C1G2 specifications with a clock frequency as low as 2.5 MHz. Nevertheless, in order to work in this region, the clock source needs to be very accurate and stable. We propose to work in the range (3.2 MHz-4.3 MHz) with looser requirements for the clock source stability and allowing a maximum jitter of 1%. An unbalanced half-T pri base transmitter allows synthesizing a more accurate BLF than with the balanced half-T pri base transmitter. However, we can observe in Fig. 7 that this gain in accuracy has a negative effect in the duty cycle. As the duty cycle constraints are really restrictive in this case, the minimum clock frequency actually required is much higher than in the previous case. In fact, the clock frequency for such a design has to be higher than 6.4 MHz. Fig. 8 shows that a C1G2 digital core with a full-T pri base transmitter obtains the best results related to the clock constraints. A wide secure operating region is found at 1/T a = 1.9 MHz with ξ max =0.5%. Moreover, with an accurate enough clock source, it is possible to satisfy the C1G2 clock signal constraints with a clock frequency as low as 1.30 MHz. Fig. 6. Clock frequency constraints for C1G2 digital core with a balanced half-T pri base transmitter.
www.intechopen.com Fig. 7. Clock frequency constraints for C1G2 digital core with an unbalanced half-T pri base transmitter. Fig. 8. Clock frequency constraints for C1G2 digital core with a full-Tpri base transmitter.

Energetic study
As explained in Section 1.2, the communication range of the system is strongly related to the power consumption of the tag. However, these power constraints are obtained assuming that the reader transmits a constant amount of power and that the tag also consumes power uniformly. None of these assumptions is true when the communication between reader and tag starts. The signal emitted from the reader is modulated, so that there is no continuous energy input at the tag. Moreover, the power consumption of the tag usually changes during the communication process. Thus, it is necessary to perform an energetic study to analyze the real behaviour of passive tags, and to understand the real limitations of the system.
The C1G2 communication protocol specifies that the forward link communication shall be ASK with a modulation depth of 90%, and the backward communication can use ASK or PSK backscattering. During the forward link the RF envelope is modulated with pulses of duration PW as shown in Fig. 9. High PW favours a clear communication. Low PW, instead, minimizes the time periods with no input power. The C1G2 standard defines the limits of acceptable PW values. Assuming that the power received during PW is negligible, the supply capacitor will supply the energy required by the rest of the tag. This will produce an energy discharge during PW. A similar effect occurs when the tag replies to the reader backscattering the received signal. The modulation in the backscattered signal is produced switching the reflection coefficient of the antenna between two states to differentiate a '0' from a '1'. Thus, the tag can communicate with the reader, but cannot receive all the energy of the input signal. The energetic discharge of the supply capacitor causes a drop in the supply voltage. This voltage drop is related with the discharged energy amount and with the value of the supply capacitor, C supply . As the circuitry of the tag requires a minimum supply voltage to work, energetic constraints can be obtained for the value of C supply . Moreover, the C1G2 standard specifies the minimum charge time of the tag, which also limits the value of C supply . This section is organized as follows. First, we present the models employed to analyze the energetic behaviour of the tag. An expression is obtained for the constraint on the maximum value of C supply and expressions that can be used to evaluate the constraint on the minimum value of C supply are presented. Next, we describe the methodology to evaluate the constraint on the minimum C supply . Finally, a case study is presented as example.

Tag model
In order to perform the energetic analysis, a simplified model of the tag is defined. The model is divided into three sub models, each of one representing a specific state of the RFID communication. The first model represents the behaviour of the tag during the charge of the supply capacitor. In this model, it is assumed that the front-end of the tag includes power on reset (POR) circuitry. This POR block is usually included in RFID front-ends in order to switch on the tag only after the supply capacitor has been charged. This way, the tag consumes almost no power during the charge period allowing a faster charge and avoiding uncontrolled activity in the tag due to low supply voltage. The second model describes the energetic behaviour of the tag when the supply capacitor is charged, all the circuits are working and a continuous power is arriving to the antenna. Finally, the third model describes the behaviour of the tag when the input wave is modulated, and times of period with no input power are present.
In order to calculate the available power in the tag, the Friis equation is used to estimate the power available in the antenna, and the power conversion efficiency factor of the tag is applied. The power available in the tag is given by where P EIRP is the equivalent isotropic radiated power emitted from the reader, λ is the wavelength of the operation frequency, r is the communication range, G TAG is the gain of the tag antenna and η is the power conversion efficiency of the tag. The characterization of the front-end includes the power conversion efficiency η, the power consumption of the tag P TAG , the required minimum supply voltage V min and the maximum allowed supply voltage V max . The front-end creates a regulated voltage at V min to supply the rest of the blocks of the tag. Moreover, the supply voltage is limited to V max , so that the technology does not break.

Charge of C supply
When the reader starts emitting power for the first time, the tag begins accumulating energy in the supply capacitor C supply. During this process, all the blocks of the tag remain switched off, so that all the incoming energy is stored in C supply. The model for this behaviour is shown in Fig. 10. It consists on a power source connected to C supply. This model is a simplified description of the behaviour of the tag during the charge process until the supply capacitor reaches the supply voltage V min. At this point, the POR switches all the modules of the tag on, and the behaviour of the tag changes. The energy stored in C supply, is related with the voltage V as follows: Given that the energy received during the time period t is equal to P IN · t, from (33), the charge time required for a specific C supply to reach V min is obtained as Introducing the maximum charge time specified in the standard in (34), and isolating C supply , the maximum C supply constraint is obtained, www.intechopen.com 3 max 2 min 21 . 5 1 0 This constraint depends on the available input power, and thus, it depends on the communication range between reader and tag.

Tag working with input power
Once V min h a s b e e n r e a c h e d , m o r e b l o c k s i n t h e tag are active and, thus, the power consumption of the tag increases. As the supply voltage of the different blocks is regulated, the power consumption of the tag does not change with the supply voltage at C supply . Thus, the power consumption of the tag is inserted in the model as a power source in the opposite direction to the input power source. Fig. 11 shows the model of the tag with all the blocks switched on and receiving constant power from the reader. Fig. 11. Tag model receiving CW from the reader.
In this case, depending on the communication range, P IN may be greater or lower than P TAG . If P IN > P TAG , V supply still receives some energy and keeps on charging. If P IN < P TAG , instead, C supply has to provide the difference, and will discharge slowly. The maximum stable communication range is the one where P IN = P TAG . Eventually, this is the power limitation seen in Section 1.2. Given that at t 0 the supply voltage had a value of V 0 , the energy accumulated in the capacitor at this moment was Considering a stable situation receiving continuous power from the reader between t 0 and t 1 , the available energy in C supply at t 1 is 10 10 () ( ) From (33), (36) and (37), the supply voltage at t 1 is obtained, 10 2 10 2( )( )

Tag working without input power
When the real communication starts, the reader modulates the RF wave. During the modulation, periods of time with no input power exist. The same happens during the backscattering of the answer. For these periods of time, the model shown in Fig. 12 is used. Both, the forward and backward modulation cause a voltage drop in C supply . Fig. 12. Tag model receiving no power from the reader.
In this case, considering a stable situation when no input energy is received from the reader between t 1 and t 2 , the energy at t 2 is given by And the supply voltage at t 2 is given by

Methodology for the energetic study
When a communication link is established, the RF wave is modulated in order to transport information, and the input power available in the tag is variable. This can cause a drop in the supply voltage. If the supply voltage drops below a minimum voltage value, V min , the tag operation can fail.
Analysing (38) and (40), we can observe that the supply voltage at a certain instant depends both on C supply and on the power consumption of the tag. When power management techniques are applied to a design, this power consumption can be very variable in time.
Additionally, different commands and forward and backward frequencies produce different profiles of power consumption in the time. There will be a certain command and certain forward and backward frequencies that yield the maximum power consumption of the tag, P max . Given a communication distance (or a specific input power in the antenna), a minimum value of the supply capacitor, C min , can be obtained that ensures that the supply voltage does not drop below V min even if P max is consumed.

Estimation of power consumption profile
where m PM is the new power management module introduced to generate the clock gating control signals for the modules. The average power consumption of the different modules of the design can be determined making them work independently at full load.
Combining the power consumption during each working state and the time spent in each of them, the profiles of the power consumption for all possible commands and configurations are obtained.

Selection of the optimum value of C supply
Equation (38) can be used to analyse the voltage drop during the charge and equation (40) during the discharge. The power profile that causes the highest voltage drop is considered to be the worst power profile. The search for the worst case shall consider the different commands and configurations. Given a value of C supply , there is a maximum value of the communication range where the supply voltage does not fall below V min in the worse case. Thus, for each value of C supply the maximum communication range can be obtained.
On the other hand, for each communication range, the constraint defined in (35) sets an upper limit on the value of the supply capacitor, C max . Taking into account the C min constraint caused by the modulation of the RF wave and the C max constraint set by the maximum charge time established by the C1G2 standard, the optimum value of C supply can be selected.

Case study
In the following example, a front-end which consumes 25 µW and has an efficiency of η =30% is assumed. The voltage limiter of the front-end is assumed to be set to 2.0 V, and the lower limit of the voltage, V min to 1.2 V. P EIRP is set to 2 W, which is the maximum power emission allowed in Europe for RFID communication at the operation frequency of 868 MHz, and G TAG is set to 1 assuming an ideal isotropic antenna. The clock signal has been set to 1.5 MHz and the typical PVT operating conditions have been used. Using the procedure described in Section 4.2.1, the power consumption in the five working states defined in Table 1 can be obtained. As the activity of the input signal depends on the forward link frequency determined by Tari, the actual power consumption of the design in RX working state also depends on the value of Tari. Similarly, the activity of the output signal depends on the BLF employed. Thus, when presenting any power consumption result of C1G2 digital cores, the configuration of the forward and backward links has to be specified. There is a lack of information about these parameters in the literature, where the results obtained are presented without further specifications. If we know the power consumption of the tag in each working state for all values of Tari and BLF, the power consumption profile of any command can be generated. As an example, Fig. 13 (a) shows the power consumption profile of a Read command with Tari = 25 µs and BLF = 40 kHz. The Read command in this example requires that the whole EPC bank (96 bits) is read. It can be observed that the power consumption changes from one working state to another.

Worst command
In order to determine the worst command, the power distribution of every command in the C1G2 standard must be obtained, as well as the voltage drop caused by them in the supply capacitor. As an example, for Tari = 25 µs and BLF = 40 kHz, Fig. 13 (b) shows the voltage drop caused by the Read command. In this case, the time that the tag has to recover energy per received symbol is greater than the recovery time per transmitted cycle. Thus, even though the power consumption in RX is higher than in TX, the voltage drop caused by the reception of the command is smaller than the voltage drop caused by the transmission of the answer. In our example, the final voltage in the supply capacitor is 1.3134 V. This is the greatest voltage drop in the supply capacitor produced by any EPC command for the design considered in our case study. This is due to the fact that the read command of the whole EPC bank is one of the longest commands received by the tag and requires the transmission of the largest amount of data. Thus, in order to characterize our digital core, the average power consumption for a Read command requesting the data of the biggest memory bank shall be used.

Worst configuration
The effects of employing different forward and backward data rates shall also be studied. The worst case Read command will be used to study the effect of the backward link configuration. However, in this command, the voltage drop caused by the forward link is mostly covered by the voltage drop caused by the backward link. Thus, results for the command with longest forward link communication, Select, will be also presented to observe the effects of Tari. Fig. 14 presents the power distribution and supply voltage drop of the worst case Read command for Tari = 25 µs and BLF = 640 kHz. If we compare these results with the ones shown in Fig. 13, we can observe that the power consumption during the TX working state reduces as lower BLFs are employed. However, reducing BLF makes the communication slower and requires that that tag stays more time in the TX working state. At the end, this produces a bigger voltage drop in the supply capacitor. In order to maximize the communication range of C1G2 RFID systems, a high BLF configuration is suggested. However, in order to characterize our digital core, results with the lowest BLF shall be used, i.e.: BLF = 40 kHz. Fig. 15 shows the power distribution and supply voltage drop of the Select command for Tari = 6.25 µs and BLF = 240 kHz. Fig. 16 presents the power distribution and supply voltage www.intechopen.com drop of the same command for Tari = 25 µs and BLF = 240 kHz. Comparing both configurations, it can be observed that for higher values of Tari the power consumption in the RX working state is reduced and, thus, the discharge of the supply capacitor slows down. However, as the forward link frequency is reduced, the time required to transmit the same number of symbols increases. Due to this fact, the supply voltage drop at the end of the operation is greater with a high Tari. Thus, the communication range of a C1G2 RFID system may be increased by configuring low Tari values. In order to ensure the correct operation of the tag in any case, the characterization of the digital core has to be done with the worst case forward link configuration, which is Tari = 25 µs. www.intechopen.com

Energetic constraints
For the worst command and worst configuration, the energetic constraints have been calculated using the model described in Section 4.1 and the methodology described in Section 4.2.2. Fig. 17 shows the obtained results for our example. On the one hand, for operation points below the C min constraint line, the supply capacitor is high enough to keep the supply voltage over V min . On the other hand, C max establishes the maximum value of the supply capacitor in order to fulfil the charge time specification. The area that is below both constraint lines is the operative region where the C1G2 standard is completely fulfilled. In this case, with values of C supply below 0.35 nF, the supply voltage always drops below V min . The maximum communication range is achieved for values of C supply above 90 nF. However, with such a capacity, the C max constraint is violated. C supply =30 nF is the point where both constraints cross. This is the value of C min that maximizes communication distance fulfilling all the energetic constraints. It can be observed in Fig. 17 that the dimensioning of C supply has a relevant impact on the actual communication range. In this case, the system would work properly with a supply capacitor of 1 nF, but the communication range would be limited by the energetic constraint to 2.8 m. Increasing C supply , the communication range is increased to 3.3 m.

Conclusion
A communication link standard poses many constraints to the clock of the digital core of a tag for proper forward-link data detection and backward-link data backscattering. For the C1G2 standard, the backward link requirements are the ones that set the most restrictive constraints. There are several frequency bands where the C1G2 specifications are fulfilled. Depending on the characteristics of the clock source, such as the average period and the maximum jitter, and on the type of transmitter, the most suitable operation point can be selected using the results presented in Section 3.
In the literature, the average power consumption is usually presented to characterize a tag. However, we have seen in Section 4 that this value is not enough. Due to the energetic behaviour of the tag, the communication range is also limited by the value of C supply . Moreover, this constraint depends on the profile of the power consumption, which changes from one command to another and from one communication mode to another. In order to obtain a complete characterization of the proposed design, a procedure as the one shown in Section 4.3 shall be followed.